(1) Field of the Invention
The present invention relates to the fabrication of semiconductor devices, and more specifically to a fabrication sequence used create metal oxide semiconductor field effect transistor, (MOSFET), devices, featuring local interconnects, and self-aligned contact, (SAC), structures.
(2) Description of Prior Art
The semiconductor industry is continually striving to improve the performance of semiconductor devices, while still attempting to reduce the cost of these same devices. These objectives have been successfully addressed by the ability of the semiconductor industry to practice micro-miniaturization, or to fabricate semiconductor devices with sub-micron features. Several fabrication disciplines, such as photolithography, as well as dry etching, have allowed micro-miniaturization to be realized. The use of more sophisticated exposure cameras, as well as the use of more sensitive photoresist films, have allowed the attainment of sub-micron images in photoresist films, to be routine achieved. In addition, the development of more advanced dry etching tools and processes, have allowed the sub-micron images, in masking photoresist films, to be successfully transferred to underlying materials used for the fabrication of semiconductor devices.
In addition to advances in semiconductor fabrication disciplines, several device structural innovations have also contributed to the quest for higher performing, lower cost, semiconductor devices. For example the use of a self-aligned contact, (SAC), procedure, allows the amount of source and drain contact area to be reduced, thus allowing smaller devices to be constructed, resulting in faster, as well as lower cost devices, to be realized. The SAC procedure, using a sub-micron ground rule, opens a sub-micron region in an insulator layer, exposing an underlying source and drain region. However only a portion of the sub-micron SAC opening is used to expose the underlying source and drain region, with the remainder of the sub-micron SAC opening overlapping an adjacent polysilicon gate structure. Therefore the source and drain contact region is smaller then the SAC opening. If the contact opening to the source and drain was to made entirely overlaying the source and drain region, the source and drain region would have to be designed larger, to accommodate the fully landed contact hole opening, thus resulting in a undesirable, larger semiconductor device.
Local interconnect structures, used as a partial, or an M.sub.D wiring level, can also be used to reduce cost, while improving the density, of advanced MOSFET devices. The use of a metal, or of a metal silicide structure, contacting, and connecting, underlying active regions of several MOSFET devices, can result in the desired cell wiring, accomplished using a short, and therefore low resistance, interconnection. This invention will describe a novel process, using silicon nitride capped, SAC processes, in conjunction with a local interconnect process, used to obtain the desired integration of MOSFET devices. Prior art such as Ramaswami, et al, in U.S. Pat. No. 5,451,545, describe a local interconnect process, but this art does not use the SAC process needed for micro-miniaturization. In addition Ramaswami, et al, describe a process for interconnecting a gate structure to a source and drain region, of a specific MOSFET device, while the present invention will describe a process for connecting elements of various MOSFET devices.